(China (Mainland))
Product Summary
The EPM7256AEQC208-10N is a high-density, high-performance device based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EPM7256AEQC208-10N operates with a 3.3-V supply voltage and provides 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. The EPM7256AEQC208-10N in the -4, -5, -6, -7, and some -10 speed grades is compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification.
Parametrics
EPM7256AEQC208-10N absolute maximum ratings: (1)Supply voltage:-0.5V to 4.6V; (2)DC input voltage:-2.0V to 5.75V; (3)DC output current, per pin:-25mA to 25mA; (4)Storage temperature:-65℃ to 150℃; (5)Ambient temperature:-65℃ to 135℃; (6)Junction temperature:135℃.
Features
EPM7256AEQC208-10N features: (1)PCI-compatible; (2)Bus-friendly architecture, including programmable slew-rate control; (3)Open-drain output option; (4)Programmable macrocell registers with individual clear, preset, clock, and clock enable controls; (5)Programmable power-up states for macrocell registers in MAX 7000AE devices; (6)Programmable power-saving mode for 50% or greater power reduction in each macrocell; (7)Configurable expander product-term distribution, allowing up to 32 product terms per macrocell; (8)Programmable security bit for protection of proprietary designs; (9)6 to 10 pin- or logic-driven output enable signals; (10)Two global clock signals with optional inversion; (11)Enhanced interconnect resources for improved routability; (12)Fast input setup times provided by a dedicated path from I/O pin to macrocell registers; (13)Programmable output slew-rate control; (14)Programmable ground pins.
Diagrams
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