ispLSI2128VE-100LT

Product Summary

The ispLSI2128VE-100LT is a High Density Programmable Logic Device. It is available in 128 and 64 I/O-pin versions. The ispLSI2128VE-100LT contains 128 Registers, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool(GRP). The ispLSI2128VE-100LT features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable.

Parametrics

ispLSI2128VE-100LT absolute maximum ratings: (1)Supply Voltage Vcc:-0.5 to +5.4V; (2)Input Voltage Applied:-0.5 to +5.6V; (3)Off-State Output Voltage Applied:-0.5 to +5.6V; (4)Storage Temperature:-65℃ to 150℃; (5)Case Temp. with Power Applied:-55℃ to 125℃; (6)Max. Junction Temp. (TJ) with Power Applied:150℃.

Features

ispLSI2128VE-100LT features: (1)6000 PLD Gates; (2)128 and 64 I/O Pin Versions, Eight Dedicated Inputs; (3)128 Registers; (4)High Speed Global Interconnect; (5)Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.; (6)Small Logic Block Size for Random Logic; (7)100% Functional, JEDEC and Pinout Compatible; (8)with ispLSI 2128V Devices; (9)fmax = 250MHz Maximum Operating Frequency; (10)tpd = 4.0ns Propagation Delay; (11)Electrically Erasable and Reprogrammable; (12)Non-Volatile; (13)100% Tested at Time of Manufacture; (14)Unused Product Term Shutdown Saves Power; (15)3.3V In-System Programmability (ISP?) Using Boundary Scan Test Access Port (TAP); (16)Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR Bus Arbitration Logic; (17)Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality; (18)Reprogram Soldered Devices for Faster Prototyping; (19)Enhanced Pin Locking Capability; (20)Three Dedicated Clock Input Pins; (21)Synchronous and Asynchronous Clocks; (22)Programmable Output Slew Rate Control; (23)Flexible Pin Placement; (24)Optimized Global Routing Pool Provides Global Interconnectivity.

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