ICS91305AMLFT

High Performance Communication Buffer, SOP8, Zero input, output delay, 3.3V ±10% operation, 5V tolerant input REF

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Price:: US $1.00~4.00 / piece [Get Latest Price]

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PartNumber:: ICS91305AMLFT

Brand:: Integrated Device Technology - IDT | Pack: SOP | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-10-20

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Product Summary

The ICS91305AMLFT is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. ICS91305AMLFT is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. The ICS91305AMLFT comes in an eight pin 150 mil SOIC package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition.

Parametrics

ICS91305AMLFT absolute maximum ratings: (1)Supply Voltage: 7.0 V; (2)Logic Inputs (Except REF): GND -0.5 V to VDD + 0.5 V; (3)Logic Input REF: GND -0.5 V to GND + 5.5 V; (4)Ambient Operating Temperature: 0℃ to +70℃; (5)Storage Temperature: -65℃ to +150℃.

Features

ICS91305AMLFT features: (1)Zero input - output delay; (2)Frequency range 10 - 133 MHz (3.3V); (3)5V tolerant input REF; (4)High loop filter bandwidth ideal for Spread Spectrum applications.; (5)Less than 200 ps Jitter between outputs; (6)Skew controlled outputs; (7)Skew less than 250 ps between outputs; (8)Available in 8 pin 150 mil SOIC & 173 mil TSSOP packages; (9)3.3V 0% operation.